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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="alphindextitle">AArch64 System Registers</h1>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-accdata_el1.html">ACCDATA_EL1</a>:
        Accelerator Data</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-actlr_el1.html">ACTLR_EL1</a>:
        Auxiliary Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-actlr_el2.html">ACTLR_EL2</a>:
        Auxiliary Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-actlr_el3.html">ACTLR_EL3</a>:
        Auxiliary Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr0_el1.html">AFSR0_EL1</a>:
        Auxiliary Fault Status Register 0 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr0_el2.html">AFSR0_EL2</a>:
        Auxiliary Fault Status Register 0 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr0_el3.html">AFSR0_EL3</a>:
        Auxiliary Fault Status Register 0 (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr1_el1.html">AFSR1_EL1</a>:
        Auxiliary Fault Status Register 1 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr1_el2.html">AFSR1_EL2</a>:
        Auxiliary Fault Status Register 1 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-afsr1_el3.html">AFSR1_EL3</a>:
        Auxiliary Fault Status Register 1 (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-aidr_el1.html">AIDR_EL1</a>:
        Auxiliary ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-allint.html">ALLINT</a>:
        All Interrupt Mask Bit</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair2_el1.html">AMAIR2_EL1</a>:
        Extended Auxiliary Memory Attribute Indirection Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair2_el2.html">AMAIR2_EL2</a>:
        Extended Auxiliary Memory Attribute Indirection Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair2_el3.html">AMAIR2_EL3</a>:
        Extended Auxiliary Memory Attribute Indirection Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair_el1.html">AMAIR_EL1</a>:
        Auxiliary Memory Attribute Indirection Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair_el2.html">AMAIR_EL2</a>:
        Auxiliary Memory Attribute Indirection Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amair_el3.html">AMAIR_EL3</a>:
        Auxiliary Memory Attribute Indirection Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcfgr_el0.html">AMCFGR_EL0</a>:
        Activity Monitors Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcg1idr_el0.html">AMCG1IDR_EL0</a>:
        Activity Monitors Counter Group 1 Identification Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcgcr_el0.html">AMCGCR_EL0</a>:
        Activity Monitors Counter Group Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcntenclr0_el0.html">AMCNTENCLR0_EL0</a>:
        Activity Monitors Count Enable Clear Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcntenclr1_el0.html">AMCNTENCLR1_EL0</a>:
        Activity Monitors Count Enable Clear Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcntenset0_el0.html">AMCNTENSET0_EL0</a>:
        Activity Monitors Count Enable Set Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcntenset1_el0.html">AMCNTENSET1_EL0</a>:
        Activity Monitors Count Enable Set Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amcr_el0.html">AMCR_EL0</a>:
        Activity Monitors Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevcntr0n_el0.html">AMEVCNTR0&lt;n&gt;_EL0</a>:
        Activity Monitors Event Counter Registers 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevcntr1n_el0.html">AMEVCNTR1&lt;n&gt;_EL0</a>:
        Activity Monitors Event Counter Registers 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevcntvoff0n_el2.html">AMEVCNTVOFF0&lt;n&gt;_EL2</a>:
        Activity Monitors Event Counter Virtual Offset Registers 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevcntvoff1n_el2.html">AMEVCNTVOFF1&lt;n&gt;_EL2</a>:
        Activity Monitors Event Counter Virtual Offset Registers 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevtyper0n_el0.html">AMEVTYPER0&lt;n&gt;_EL0</a>:
        Activity Monitors Event Type Registers 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amevtyper1n_el0.html">AMEVTYPER1&lt;n&gt;_EL0</a>:
        Activity Monitors Event Type Registers 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-amuserenr_el0.html">AMUSERENR_EL0</a>:
        Activity Monitors User Enable Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apdakeyhi_el1.html">APDAKeyHi_EL1</a>:
        Pointer Authentication Key A for Data (bits[127:64]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apdakeylo_el1.html">APDAKeyLo_EL1</a>:
        Pointer Authentication Key A for Data (bits[63:0]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apdbkeyhi_el1.html">APDBKeyHi_EL1</a>:
        Pointer Authentication Key B for Data (bits[127:64]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apdbkeylo_el1.html">APDBKeyLo_EL1</a>:
        Pointer Authentication Key B for Data (bits[63:0]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apgakeyhi_el1.html">APGAKeyHi_EL1</a>:
        Pointer Authentication Key A for Code (bits[127:64]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apgakeylo_el1.html">APGAKeyLo_EL1</a>:
        Pointer Authentication Key A for Code (bits[63:0]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apiakeyhi_el1.html">APIAKeyHi_EL1</a>:
        Pointer Authentication Key A for Instruction (bits[127:64]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apiakeylo_el1.html">APIAKeyLo_EL1</a>:
        Pointer Authentication Key A for Instruction (bits[63:0]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apibkeyhi_el1.html">APIBKeyHi_EL1</a>:
        Pointer Authentication Key B for Instruction (bits[127:64]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-apibkeylo_el1.html">APIBKeyLo_EL1</a>:
        Pointer Authentication Key B for Instruction (bits[63:0]) </span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbcr_el1.html">BRBCR_EL1</a>:
        Branch Record Buffer Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbcr_el2.html">BRBCR_EL2</a>:
        Branch Record Buffer Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbfcr_el1.html">BRBFCR_EL1</a>:
        Branch Record Buffer Function Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbidr0_el1.html">BRBIDR0_EL1</a>:
        Branch Record Buffer ID0 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbinfn_el1.html">BRBINF&lt;n&gt;_EL1</a>:
        Branch Record Buffer Information Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbinfinj_el1.html">BRBINFINJ_EL1</a>:
        Branch Record Buffer Information Injection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbsrcn_el1.html">BRBSRC&lt;n&gt;_EL1</a>:
        Branch Record Buffer Source Address Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbsrcinj_el1.html">BRBSRCINJ_EL1</a>:
        Branch Record Buffer Source Address Injection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbtgtn_el1.html">BRBTGT&lt;n&gt;_EL1</a>:
        Branch Record Buffer Target Address Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbtgtinj_el1.html">BRBTGTINJ_EL1</a>:
        Branch Record Buffer Target Address Injection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-brbts_el1.html">BRBTS_EL1</a>:
        Branch Record Buffer Timestamp Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ccsidr2_el1.html">CCSIDR2_EL1</a>:
        Current Cache Size ID Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ccsidr_el1.html">CCSIDR_EL1</a>:
        Current Cache Size ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-clidr_el1.html">CLIDR_EL1</a>:
        Cache Level ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntfrq_el0.html">CNTFRQ_EL0</a>:
        Counter-timer Frequency Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthctl_el2.html">CNTHCTL_EL2</a>:
        Counter-timer Hypervisor Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthps_ctl_el2.html">CNTHPS_CTL_EL2</a>:
        Counter-timer Secure Physical Timer Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthps_cval_el2.html">CNTHPS_CVAL_EL2</a>:
        Counter-timer Secure Physical Timer CompareValue Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthps_tval_el2.html">CNTHPS_TVAL_EL2</a>:
        Counter-timer Secure Physical Timer TimerValue Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthp_ctl_el2.html">CNTHP_CTL_EL2</a>:
        Counter-timer Hypervisor Physical Timer Control register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthp_cval_el2.html">CNTHP_CVAL_EL2</a>:
        Counter-timer Physical Timer CompareValue register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthp_tval_el2.html">CNTHP_TVAL_EL2</a>:
        Counter-timer Physical Timer TimerValue register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthvs_ctl_el2.html">CNTHVS_CTL_EL2</a>:
        Counter-timer Secure Virtual Timer Control register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthvs_cval_el2.html">CNTHVS_CVAL_EL2</a>:
        Counter-timer Secure Virtual Timer CompareValue register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthvs_tval_el2.html">CNTHVS_TVAL_EL2</a>:
        Counter-timer Secure Virtual Timer TimerValue register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthv_ctl_el2.html">CNTHV_CTL_EL2</a>:
        Counter-timer Virtual Timer Control register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthv_cval_el2.html">CNTHV_CVAL_EL2</a>:
        Counter-timer Virtual Timer CompareValue register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cnthv_tval_el2.html">CNTHV_TVAL_EL2</a>:
        Counter-timer Virtual Timer TimerValue Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntkctl_el1.html">CNTKCTL_EL1</a>:
        Counter-timer Kernel Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntpctss_el0.html">CNTPCTSS_EL0</a>:
        Counter-timer Self-Synchronized Physical Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntpct_el0.html">CNTPCT_EL0</a>:
        Counter-timer Physical Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntpoff_el2.html">CNTPOFF_EL2</a>:
        Counter-timer Physical Offset Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntps_ctl_el1.html">CNTPS_CTL_EL1</a>:
        Counter-timer Physical Secure Timer Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntps_cval_el1.html">CNTPS_CVAL_EL1</a>:
        Counter-timer Physical Secure Timer CompareValue Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntps_tval_el1.html">CNTPS_TVAL_EL1</a>:
        Counter-timer Physical Secure Timer TimerValue register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntp_ctl_el0.html">CNTP_CTL_EL0</a>:
        Counter-timer Physical Timer Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntp_cval_el0.html">CNTP_CVAL_EL0</a>:
        Counter-timer Physical Timer CompareValue Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntp_tval_el0.html">CNTP_TVAL_EL0</a>:
        Counter-timer Physical Timer TimerValue Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntvctss_el0.html">CNTVCTSS_EL0</a>:
        Counter-timer Self-Synchronized Virtual Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntvct_el0.html">CNTVCT_EL0</a>:
        Counter-timer Virtual Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntvoff_el2.html">CNTVOFF_EL2</a>:
        Counter-timer Virtual Offset Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntv_ctl_el0.html">CNTV_CTL_EL0</a>:
        Counter-timer Virtual Timer Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntv_cval_el0.html">CNTV_CVAL_EL0</a>:
        Counter-timer Virtual Timer CompareValue Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cntv_tval_el0.html">CNTV_TVAL_EL0</a>:
        Counter-timer Virtual Timer TimerValue Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-contextidr_el1.html">CONTEXTIDR_EL1</a>:
        Context ID Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-contextidr_el2.html">CONTEXTIDR_EL2</a>:
        Context ID Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cpacr_el1.html">CPACR_EL1</a>:
        Architectural Feature Access Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cptr_el2.html">CPTR_EL2</a>:
        Architectural Feature Trap Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-cptr_el3.html">CPTR_EL3</a>:
        Architectural Feature Trap Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-csselr_el1.html">CSSELR_EL1</a>:
        Cache Size Selection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ctr_el0.html">CTR_EL0</a>:
        Cache Type Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-currentel.html">CurrentEL</a>:
        Current Exception Level</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dacr32_el2.html">DACR32_EL2</a>:
        Domain Access Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-daif.html">DAIF</a>:
        Interrupt Mask Bits</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgauthstatus_el1.html">DBGAUTHSTATUS_EL1</a>:
        Debug Authentication Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgbcrn_el1.html">DBGBCR&lt;n&gt;_EL1</a>:
        Debug Breakpoint Control Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgbvrn_el1.html">DBGBVR&lt;n&gt;_EL1</a>:
        Debug Breakpoint Value Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgclaimclr_el1.html">DBGCLAIMCLR_EL1</a>:
        Debug CLAIM Tag Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgclaimset_el1.html">DBGCLAIMSET_EL1</a>:
        Debug CLAIM Tag Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgdtrrx_el0.html">DBGDTRRX_EL0</a>:
        Debug Data Transfer Register, Receive</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgdtrtx_el0.html">DBGDTRTX_EL0</a>:
        Debug Data Transfer Register, Transmit</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgdtr_el0.html">DBGDTR_EL0</a>:
        Debug Data Transfer Register, half-duplex</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgprcr_el1.html">DBGPRCR_EL1</a>:
        Debug Power Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgvcr32_el2.html">DBGVCR32_EL2</a>:
        Debug Vector Catch Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgwcrn_el1.html">DBGWCR&lt;n&gt;_EL1</a>:
        Debug Watchpoint Control Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dbgwvrn_el1.html">DBGWVR&lt;n&gt;_EL1</a>:
        Debug Watchpoint Value Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dczid_el0.html">DCZID_EL0</a>:
        Data Cache Zero ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-disr_el1.html">DISR_EL1</a>:
        Deferred Interrupt Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dit.html">DIT</a>:
        Data Independent Timing</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dlr_el0.html">DLR_EL0</a>:
        Debug Link Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-dspsr_el0.html">DSPSR_EL0</a>:
        Debug Saved Program Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-elr_el1.html">ELR_EL1</a>:
        Exception Link Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-elr_el2.html">ELR_EL2</a>:
        Exception Link Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-elr_el3.html">ELR_EL3</a>:
        Exception Link Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erridr_el1.html">ERRIDR_EL1</a>:
        Error Record ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-errselr_el1.html">ERRSELR_EL1</a>:
        Error Record Select Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxaddr_el1.html">ERXADDR_EL1</a>:
        Selected Error Record Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxctlr_el1.html">ERXCTLR_EL1</a>:
        Selected Error Record Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxfr_el1.html">ERXFR_EL1</a>:
        Selected Error Record Feature Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxgsr_el1.html">ERXGSR_EL1</a>:
        Selected Error Record Group Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxmisc0_el1.html">ERXMISC0_EL1</a>:
        Selected Error Record Miscellaneous Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxmisc1_el1.html">ERXMISC1_EL1</a>:
        Selected Error Record Miscellaneous Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxmisc2_el1.html">ERXMISC2_EL1</a>:
        Selected Error Record Miscellaneous Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxmisc3_el1.html">ERXMISC3_EL1</a>:
        Selected Error Record Miscellaneous Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxpfgcdn_el1.html">ERXPFGCDN_EL1</a>:
        Selected Pseudo-fault Generation Countdown Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxpfgctl_el1.html">ERXPFGCTL_EL1</a>:
        Selected Pseudo-fault Generation Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxpfgf_el1.html">ERXPFGF_EL1</a>:
        Selected Pseudo-fault Generation Feature Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-erxstatus_el1.html">ERXSTATUS_EL1</a>:
        Selected Error Record Primary Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-esr_el1.html">ESR_EL1</a>:
        Exception Syndrome Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-esr_el2.html">ESR_EL2</a>:
        Exception Syndrome Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-esr_el3.html">ESR_EL3</a>:
        Exception Syndrome Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-far_el1.html">FAR_EL1</a>:
        Fault Address Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-far_el2.html">FAR_EL2</a>:
        Fault Address Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-far_el3.html">FAR_EL3</a>:
        Fault Address Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-fpcr.html">FPCR</a>:
        Floating-point Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-fpexc32_el2.html">FPEXC32_EL2</a>:
        Floating-Point Exception Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-fpsr.html">FPSR</a>:
        Floating-point Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcr_el1.html">GCR_EL1</a>:
        Tag Control Register.</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcscre0_el1.html">GCSCRE0_EL1</a>:
        Guarded Control Stack Control (EL0)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcscr_el1.html">GCSCR_EL1</a>:
        Guarded Control Stack Control (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcscr_el2.html">GCSCR_EL2</a>:
        Guarded Control Stack Control (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcscr_el3.html">GCSCR_EL3</a>:
        Guarded Control Stack Control (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcspr_el0.html">GCSPR_EL0</a>:
        Guarded Control Stack Pointer (EL0)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcspr_el1.html">GCSPR_EL1</a>:
        Guarded Control Stack Pointer (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcspr_el2.html">GCSPR_EL2</a>:
        Guarded Control Stack Pointer (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gcspr_el3.html">GCSPR_EL3</a>:
        Guarded Control Stack Pointer (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gmid_el1.html">GMID_EL1</a>:
        Multiple tag transfer ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gpccr_el3.html">GPCCR_EL3</a>:
        Granule Protection Check Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-gptbr_el3.html">GPTBR_EL3</a>:
        Granule Protection Table Base Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hacr_el2.html">HACR_EL2</a>:
        Hypervisor Auxiliary Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hafgrtr_el2.html">HAFGRTR_EL2</a>:
        Hypervisor Activity Monitors Fine-Grained Read Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hcrx_el2.html">HCRX_EL2</a>:
        Extended Hypervisor Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hcr_el2.html">HCR_EL2</a>:
        Hypervisor Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hdfgrtr2_el2.html">HDFGRTR2_EL2</a>:
        Hypervisor Debug Fine-Grained Read Trap Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hdfgrtr_el2.html">HDFGRTR_EL2</a>:
        Hypervisor Debug Fine-Grained Read Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hdfgwtr2_el2.html">HDFGWTR2_EL2</a>:
        Hypervisor Debug Fine-Grained Write Trap Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hdfgwtr_el2.html">HDFGWTR_EL2</a>:
        Hypervisor Debug Fine-Grained Write Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgitr2_el2.html">HFGITR2_EL2</a>:
        Hypervisor Fine-Grained Instruction Trap Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgitr_el2.html">HFGITR_EL2</a>:
        Hypervisor Fine-Grained Instruction Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgrtr2_el2.html">HFGRTR2_EL2</a>:
        Hypervisor Fine-Grained Read Trap Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgrtr_el2.html">HFGRTR_EL2</a>:
        Hypervisor Fine-Grained Read Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgwtr2_el2.html">HFGWTR2_EL2</a>:
        Hypervisor Fine-Grained Write Trap Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hfgwtr_el2.html">HFGWTR_EL2</a>:
        Hypervisor Fine-Grained Write Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hpfar_el2.html">HPFAR_EL2</a>:
        Hypervisor IPA Fault Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-hstr_el2.html">HSTR_EL2</a>:
        Hypervisor System Trap Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_ap0rn_el1.html">ICC_AP0R&lt;n&gt;_EL1</a>:
        Interrupt Controller Active Priorities Group 0 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_ap1rn_el1.html">ICC_AP1R&lt;n&gt;_EL1</a>:
        Interrupt Controller Active Priorities Group 1 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_asgi1r_el1.html">ICC_ASGI1R_EL1</a>:
        Interrupt Controller Alias Software Generated Interrupt Group 1 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_bpr0_el1.html">ICC_BPR0_EL1</a>:
        Interrupt Controller Binary Point Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_bpr1_el1.html">ICC_BPR1_EL1</a>:
        Interrupt Controller Binary Point Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_ctlr_el1.html">ICC_CTLR_EL1</a>:
        Interrupt Controller Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_ctlr_el3.html">ICC_CTLR_EL3</a>:
        Interrupt Controller Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_dir_el1.html">ICC_DIR_EL1</a>:
        Interrupt Controller Deactivate Interrupt Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_eoir0_el1.html">ICC_EOIR0_EL1</a>:
        Interrupt Controller End Of Interrupt Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_eoir1_el1.html">ICC_EOIR1_EL1</a>:
        Interrupt Controller End Of Interrupt Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_hppir0_el1.html">ICC_HPPIR0_EL1</a>:
        Interrupt Controller Highest Priority Pending Interrupt Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_hppir1_el1.html">ICC_HPPIR1_EL1</a>:
        Interrupt Controller Highest Priority Pending Interrupt Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_iar0_el1.html">ICC_IAR0_EL1</a>:
        Interrupt Controller Interrupt Acknowledge Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_iar1_el1.html">ICC_IAR1_EL1</a>:
        Interrupt Controller Interrupt Acknowledge Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_igrpen0_el1.html">ICC_IGRPEN0_EL1</a>:
        Interrupt Controller Interrupt Group 0 Enable register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_igrpen1_el1.html">ICC_IGRPEN1_EL1</a>:
        Interrupt Controller Interrupt Group 1 Enable register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_igrpen1_el3.html">ICC_IGRPEN1_EL3</a>:
        Interrupt Controller Interrupt Group 1 Enable register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_nmiar1_el1.html">ICC_NMIAR1_EL1</a>:
        Interrupt Controller Non-maskable Interrupt Acknowledge Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_pmr_el1.html">ICC_PMR_EL1</a>:
        Interrupt Controller Interrupt Priority Mask Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_rpr_el1.html">ICC_RPR_EL1</a>:
        Interrupt Controller Running Priority Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_sgi0r_el1.html">ICC_SGI0R_EL1</a>:
        Interrupt Controller Software Generated Interrupt Group 0 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_sgi1r_el1.html">ICC_SGI1R_EL1</a>:
        Interrupt Controller Software Generated Interrupt Group 1 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_sre_el1.html">ICC_SRE_EL1</a>:
        Interrupt Controller System Register Enable Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_sre_el2.html">ICC_SRE_EL2</a>:
        Interrupt Controller System Register Enable Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icc_sre_el3.html">ICC_SRE_EL3</a>:
        Interrupt Controller System Register Enable Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_ap0rn_el2.html">ICH_AP0R&lt;n&gt;_EL2</a>:
        Interrupt Controller Hyp Active Priorities Group 0 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_ap1rn_el2.html">ICH_AP1R&lt;n&gt;_EL2</a>:
        Interrupt Controller Hyp Active Priorities Group 1 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_eisr_el2.html">ICH_EISR_EL2</a>:
        Interrupt Controller End of Interrupt Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_elrsr_el2.html">ICH_ELRSR_EL2</a>:
        Interrupt Controller Empty List Register Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_hcr_el2.html">ICH_HCR_EL2</a>:
        Interrupt Controller Hyp Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_lrn_el2.html">ICH_LR&lt;n&gt;_EL2</a>:
        Interrupt Controller List Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_misr_el2.html">ICH_MISR_EL2</a>:
        Interrupt Controller Maintenance Interrupt State Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_vmcr_el2.html">ICH_VMCR_EL2</a>:
        Interrupt Controller Virtual Machine Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ich_vtr_el2.html">ICH_VTR_EL2</a>:
        Interrupt Controller VGIC Type Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_ap0rn_el1.html">ICV_AP0R&lt;n&gt;_EL1</a>:
        Interrupt Controller Virtual Active Priorities Group 0 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_ap1rn_el1.html">ICV_AP1R&lt;n&gt;_EL1</a>:
        Interrupt Controller Virtual Active Priorities Group 1 Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_bpr0_el1.html">ICV_BPR0_EL1</a>:
        Interrupt Controller Virtual Binary Point Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_bpr1_el1.html">ICV_BPR1_EL1</a>:
        Interrupt Controller Virtual Binary Point Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_ctlr_el1.html">ICV_CTLR_EL1</a>:
        Interrupt Controller Virtual Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_dir_el1.html">ICV_DIR_EL1</a>:
        Interrupt Controller Deactivate Virtual Interrupt Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_eoir0_el1.html">ICV_EOIR0_EL1</a>:
        Interrupt Controller Virtual End Of Interrupt Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_eoir1_el1.html">ICV_EOIR1_EL1</a>:
        Interrupt Controller Virtual End Of Interrupt Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_hppir0_el1.html">ICV_HPPIR0_EL1</a>:
        Interrupt Controller Virtual Highest Priority Pending Interrupt Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_hppir1_el1.html">ICV_HPPIR1_EL1</a>:
        Interrupt Controller Virtual Highest Priority Pending Interrupt Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_iar0_el1.html">ICV_IAR0_EL1</a>:
        Interrupt Controller Virtual Interrupt Acknowledge Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_iar1_el1.html">ICV_IAR1_EL1</a>:
        Interrupt Controller Virtual Interrupt Acknowledge Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_igrpen0_el1.html">ICV_IGRPEN0_EL1</a>:
        Interrupt Controller Virtual Interrupt Group 0 Enable register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_igrpen1_el1.html">ICV_IGRPEN1_EL1</a>:
        Interrupt Controller Virtual Interrupt Group 1 Enable register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_nmiar1_el1.html">ICV_NMIAR1_EL1</a>:
        Interrupt Controller Virtual Non-maskable Interrupt Acknowledge Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_pmr_el1.html">ICV_PMR_EL1</a>:
        Interrupt Controller Virtual Interrupt Priority Mask Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-icv_rpr_el1.html">ICV_RPR_EL1</a>:
        Interrupt Controller Virtual Running Priority Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64afr0_el1.html">ID_AA64AFR0_EL1</a>:
        AArch64 Auxiliary Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64afr1_el1.html">ID_AA64AFR1_EL1</a>:
        AArch64 Auxiliary Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64dfr0_el1.html">ID_AA64DFR0_EL1</a>:
        AArch64 Debug Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64dfr1_el1.html">ID_AA64DFR1_EL1</a>:
        AArch64 Debug Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64isar0_el1.html">ID_AA64ISAR0_EL1</a>:
        AArch64 Instruction Set Attribute Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64isar1_el1.html">ID_AA64ISAR1_EL1</a>:
        AArch64 Instruction Set Attribute Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64isar2_el1.html">ID_AA64ISAR2_EL1</a>:
        AArch64 Instruction Set Attribute Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64mmfr0_el1.html">ID_AA64MMFR0_EL1</a>:
        AArch64 Memory Model Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64mmfr1_el1.html">ID_AA64MMFR1_EL1</a>:
        AArch64 Memory Model Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64mmfr2_el1.html">ID_AA64MMFR2_EL1</a>:
        AArch64 Memory Model Feature Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64mmfr3_el1.html">ID_AA64MMFR3_EL1</a>:
        AArch64 Memory Model Feature Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64mmfr4_el1.html">ID_AA64MMFR4_EL1</a>:
        AArch64 Memory Model Feature Register 4</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64pfr0_el1.html">ID_AA64PFR0_EL1</a>:
        AArch64 Processor Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64pfr1_el1.html">ID_AA64PFR1_EL1</a>:
        AArch64 Processor Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64pfr2_el1.html">ID_AA64PFR2_EL1</a>:
        AArch64 Processor Feature Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64smfr0_el1.html">ID_AA64SMFR0_EL1</a>:
        SME Feature ID Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_aa64zfr0_el1.html">ID_AA64ZFR0_EL1</a>:
        SVE Feature ID Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_afr0_el1.html">ID_AFR0_EL1</a>:
        AArch32 Auxiliary Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_dfr0_el1.html">ID_DFR0_EL1</a>:
        AArch32 Debug Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_dfr1_el1.html">ID_DFR1_EL1</a>:
        Debug Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar0_el1.html">ID_ISAR0_EL1</a>:
        AArch32 Instruction Set Attribute Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar1_el1.html">ID_ISAR1_EL1</a>:
        AArch32 Instruction Set Attribute Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar2_el1.html">ID_ISAR2_EL1</a>:
        AArch32 Instruction Set Attribute Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar3_el1.html">ID_ISAR3_EL1</a>:
        AArch32 Instruction Set Attribute Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar4_el1.html">ID_ISAR4_EL1</a>:
        AArch32 Instruction Set Attribute Register 4</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar5_el1.html">ID_ISAR5_EL1</a>:
        AArch32 Instruction Set Attribute Register 5</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_isar6_el1.html">ID_ISAR6_EL1</a>:
        AArch32 Instruction Set Attribute Register 6</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr0_el1.html">ID_MMFR0_EL1</a>:
        AArch32 Memory Model Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr1_el1.html">ID_MMFR1_EL1</a>:
        AArch32 Memory Model Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr2_el1.html">ID_MMFR2_EL1</a>:
        AArch32 Memory Model Feature Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr3_el1.html">ID_MMFR3_EL1</a>:
        AArch32 Memory Model Feature Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr4_el1.html">ID_MMFR4_EL1</a>:
        AArch32 Memory Model Feature Register 4</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_mmfr5_el1.html">ID_MMFR5_EL1</a>:
        AArch32 Memory Model Feature Register 5</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_pfr0_el1.html">ID_PFR0_EL1</a>:
        AArch32 Processor Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_pfr1_el1.html">ID_PFR1_EL1</a>:
        AArch32 Processor Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-id_pfr2_el1.html">ID_PFR2_EL1</a>:
        AArch32 Processor Feature Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ifsr32_el2.html">IFSR32_EL2</a>:
        Instruction Fault Status Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-isr_el1.html">ISR_EL1</a>:
        Interrupt Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-lorc_el1.html">LORC_EL1</a>:
        LORegion Control (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-lorea_el1.html">LOREA_EL1</a>:
        LORegion End Address (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-lorid_el1.html">LORID_EL1</a>:
        LORegionID (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-lorn_el1.html">LORN_EL1</a>:
        LORegion Number (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-lorsa_el1.html">LORSA_EL1</a>:
        LORegion Start Address (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair2_el1.html">MAIR2_EL1</a>:
        Extended Memory Attribute Indirection Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair2_el2.html">MAIR2_EL2</a>:
        Extended Memory Attribute Indirection Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair2_el3.html">MAIR2_EL3</a>:
        Extended Memory Attribute Indirection Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair_el1.html">MAIR_EL1</a>:
        Memory Attribute Indirection Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair_el2.html">MAIR_EL2</a>:
        Memory Attribute Indirection Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mair_el3.html">MAIR_EL3</a>:
        Memory Attribute Indirection Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdccint_el1.html">MDCCINT_EL1</a>:
        Monitor DCC Interrupt Enable Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdccsr_el0.html">MDCCSR_EL0</a>:
        Monitor DCC Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdcr_el2.html">MDCR_EL2</a>:
        Monitor Debug Configuration Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdcr_el3.html">MDCR_EL3</a>:
        Monitor Debug Configuration Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdrar_el1.html">MDRAR_EL1</a>:
        Monitor Debug ROM Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdscr_el1.html">MDSCR_EL1</a>:
        Monitor Debug System Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mdselr_el1.html">MDSELR_EL1</a>:
        Breakpoint and Watchpoint Selection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecidr_el2.html">MECIDR_EL2</a>:
        MEC Identification Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecid_a0_el2.html">MECID_A0_EL2</a>:
        Alternate MECID for EL2 and EL2&amp;0 translation regimes</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecid_a1_el2.html">MECID_A1_EL2</a>:
        Alternate MECID for EL2&amp;0 translation regimes.</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecid_p0_el2.html">MECID_P0_EL2</a>:
        Primary MECID for EL2 and EL2&amp;0 translation regimes</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecid_p1_el2.html">MECID_P1_EL2</a>:
        Primary MECID for EL2&amp;0 translation regimes</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mecid_rl_a_el3.html">MECID_RL_A_EL3</a>:
        Realm PA space Alternate MECID for EL3 stage 1 translation regime</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mfar_el3.html">MFAR_EL3</a>:
        Physical Fault Address Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-midr_el1.html">MIDR_EL1</a>:
        Main ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpam0_el1.html">MPAM0_EL1</a>:
        MPAM0 Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpam1_el1.html">MPAM1_EL1</a>:
        MPAM1 Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpam2_el2.html">MPAM2_EL2</a>:
        MPAM2 Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpam3_el3.html">MPAM3_EL3</a>:
        MPAM3 Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamhcr_el2.html">MPAMHCR_EL2</a>:
        MPAM Hypervisor Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamidr_el1.html">MPAMIDR_EL1</a>:
        MPAM ID Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamsm_el1.html">MPAMSM_EL1</a>:
        MPAM Streaming Mode Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm0_el2.html">MPAMVPM0_EL2</a>:
        MPAM Virtual PARTID Mapping Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm1_el2.html">MPAMVPM1_EL2</a>:
        MPAM Virtual PARTID Mapping Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm2_el2.html">MPAMVPM2_EL2</a>:
        MPAM Virtual PARTID Mapping Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm3_el2.html">MPAMVPM3_EL2</a>:
        MPAM Virtual PARTID Mapping Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm4_el2.html">MPAMVPM4_EL2</a>:
        MPAM Virtual PARTID Mapping Register 4</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm5_el2.html">MPAMVPM5_EL2</a>:
        MPAM Virtual PARTID Mapping Register 5</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm6_el2.html">MPAMVPM6_EL2</a>:
        MPAM Virtual PARTID Mapping Register 6</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpm7_el2.html">MPAMVPM7_EL2</a>:
        MPAM Virtual PARTID Mapping Register 7</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpamvpmv_el2.html">MPAMVPMV_EL2</a>:
        MPAM Virtual Partition Mapping Valid Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mpidr_el1.html">MPIDR_EL1</a>:
        Multiprocessor Affinity Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mvfr0_el1.html">MVFR0_EL1</a>:
        AArch32 Media and VFP Feature Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mvfr1_el1.html">MVFR1_EL1</a>:
        AArch32 Media and VFP Feature Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-mvfr2_el1.html">MVFR2_EL1</a>:
        AArch32 Media and VFP Feature Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-nzcv.html">NZCV</a>:
        Condition Flags</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-osdlr_el1.html">OSDLR_EL1</a>:
        OS Double Lock Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-osdtrrx_el1.html">OSDTRRX_EL1</a>:
        OS Lock Data Transfer Register, Receive</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-osdtrtx_el1.html">OSDTRTX_EL1</a>:
        OS Lock Data Transfer Register, Transmit</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-oseccr_el1.html">OSECCR_EL1</a>:
        OS Lock Exception Catch Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-oslar_el1.html">OSLAR_EL1</a>:
        OS Lock Access Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-oslsr_el1.html">OSLSR_EL1</a>:
        OS Lock Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pan.html">PAN</a>:
        Privileged Access Never</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-par_el1.html">PAR_EL1</a>:
        Physical Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pfar_el1.html">PFAR_EL1</a>:
        Physical Fault Address Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pfar_el2.html">PFAR_EL2</a>:
        Physical Fault Address Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pire0_el1.html">PIRE0_EL1</a>:
        Permission Indirection Register 0 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pire0_el2.html">PIRE0_EL2</a>:
        Permission Indirection Register 0 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pir_el1.html">PIR_EL1</a>:
        Permission Indirection Register 1 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pir_el2.html">PIR_EL2</a>:
        Permission Indirection Register 2 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pir_el3.html">PIR_EL3</a>:
         Permission Indirection Register 3 (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pm.html">PM</a>:
        PMU Exception Mask</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmbidr_el1.html">PMBIDR_EL1</a>:
        Profiling Buffer ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmblimitr_el1.html">PMBLIMITR_EL1</a>:
        Profiling Buffer Limit Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmbptr_el1.html">PMBPTR_EL1</a>:
        Profiling Buffer Write Pointer Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmbsr_el1.html">PMBSR_EL1</a>:
        Profiling Buffer Status/syndrome Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmccfiltr_el0.html">PMCCFILTR_EL0</a>:
        Performance Monitors Cycle Count Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmccntr_el0.html">PMCCNTR_EL0</a>:
        Performance Monitors Cycle Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmccntsvr_el1.html">PMCCNTSVR_EL1</a>:
        Performance Monitors Cycle Count Saved Value Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmceid0_el0.html">PMCEID0_EL0</a>:
        Performance Monitors Common Event Identification Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmceid1_el0.html">PMCEID1_EL0</a>:
        Performance Monitors Common Event Identification Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmcntenclr_el0.html">PMCNTENCLR_EL0</a>:
        Performance Monitors Count Enable Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmcntenset_el0.html">PMCNTENSET_EL0</a>:
        Performance Monitors Count Enable Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmcr_el0.html">PMCR_EL0</a>:
        Performance Monitors Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmecr_el1.html">PMECR_EL1</a>:
        Performance Monitors Extended Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmevcntrn_el0.html">PMEVCNTR&lt;n&gt;_EL0</a>:
        Performance Monitors Event Count Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmevcntsvrn_el1.html">PMEVCNTSVR&lt;n&gt;_EL1</a>:
        Performance Monitors Event Count Saved Value Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmevtypern_el0.html">PMEVTYPER&lt;n&gt;_EL0</a>:
        Performance Monitors Event Type Registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmiar_el1.html">PMIAR_EL1</a>:
        Performance Monitors Instruction Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmicfiltr_el0.html">PMICFILTR_EL0</a>:
        Performance Monitors Instruction Counter Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmicntr_el0.html">PMICNTR_EL0</a>:
        Performance Monitors Instruction Counter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmicntsvr_el1.html">PMICNTSVR_EL1</a>:
        Performance Monitors Instruction Count Saved Value Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmintenclr_el1.html">PMINTENCLR_EL1</a>:
        Performance Monitors Interrupt Enable Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmintenset_el1.html">PMINTENSET_EL1</a>:
        Performance Monitors Interrupt Enable Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmmir_el1.html">PMMIR_EL1</a>:
        Performance Monitors Machine Identification Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmovsclr_el0.html">PMOVSCLR_EL0</a>:
        Performance Monitors Overflow Flag Status Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmovsset_el0.html">PMOVSSET_EL0</a>:
        Performance Monitors Overflow Flag Status Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmscr_el1.html">PMSCR_EL1</a>:
        Statistical Profiling Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmscr_el2.html">PMSCR_EL2</a>:
        Statistical Profiling Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsdsfr_el1.html">PMSDSFR_EL1</a>:
        Sampling Data Source Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmselr_el0.html">PMSELR_EL0</a>:
        Performance Monitors Event Counter Selection Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsevfr_el1.html">PMSEVFR_EL1</a>:
        Sampling Event Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsfcr_el1.html">PMSFCR_EL1</a>:
        Sampling Filter Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsicr_el1.html">PMSICR_EL1</a>:
        Sampling Interval Counter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsidr_el1.html">PMSIDR_EL1</a>:
        Sampling Profiling ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsirr_el1.html">PMSIRR_EL1</a>:
        Sampling Interval Reload Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmslatfr_el1.html">PMSLATFR_EL1</a>:
        Sampling Latency Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsnevfr_el1.html">PMSNEVFR_EL1</a>:
        Sampling Inverted Event Filter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmsscr_el1.html">PMSSCR_EL1</a>:
        Performance Monitors Snapshot Status and Capture Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmswinc_el0.html">PMSWINC_EL0</a>:
        Performance Monitors Software Increment Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmuacr_el1.html">PMUACR_EL1</a>:
        Performance Monitors User Access Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmuserenr_el0.html">PMUSERENR_EL0</a>:
        Performance Monitors User Enable Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmxevcntr_el0.html">PMXEVCNTR_EL0</a>:
        Performance Monitors Selected Event Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmxevtyper_el0.html">PMXEVTYPER_EL0</a>:
        Performance Monitors Selected Event Type Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-pmzr_el0.html">PMZR_EL0</a>:
        Performance Monitors Zero with Mask</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-por_el0.html">POR_EL0</a>:
        Permission Overlay Register 0 (EL0)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-por_el1.html">POR_EL1</a>:
        Permission Overlay Register 1 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-por_el2.html">POR_EL2</a>:
        Permission Overlay Register 2 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-por_el3.html">POR_EL3</a>:
        Permission Overlay Register 3 (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rcwmask_el1.html">RCWMASK_EL1</a>:
        Read Check Write Instruction Mask (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rcwsmask_el1.html">RCWSMASK_EL1</a>:
        Software Read Check Write Instruction Mask (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-revidr_el1.html">REVIDR_EL1</a>:
        Revision ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rgsr_el1.html">RGSR_EL1</a>:
        Random Allocation Tag Seed Register.</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rmr_el1.html">RMR_EL1</a>:
        Reset Management Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rmr_el2.html">RMR_EL2</a>:
        Reset Management Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rmr_el3.html">RMR_EL3</a>:
        Reset Management Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rndr.html">RNDR</a>:
        Random Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rndrrs.html">RNDRRS</a>:
        Reseeded Random Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rvbar_el1.html">RVBAR_EL1</a>:
        Reset Vector Base Address Register (if EL2 and EL3 not implemented)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rvbar_el2.html">RVBAR_EL2</a>:
        Reset Vector Base Address Register (if EL3 not implemented)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-rvbar_el3.html">RVBAR_EL3</a>:
        Reset Vector Base Address Register (if EL3 implemented)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-s2pir_el2.html">S2PIR_EL2</a>:
        Stage 2 Permission Indirection Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-s2por_el1.html">S2POR_EL1</a>:
        Stage 2 Permission Overlay Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-s3_op1_cn_cm_op2.html">S3_&lt;op1&gt;_&lt;Cn&gt;_&lt;Cm&gt;_&lt;op2&gt;</a>:
        IMPLEMENTATION DEFINED registers</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-scr_el3.html">SCR_EL3</a>:
        Secure Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr2_el1.html">SCTLR2_EL1</a>:
        System Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr2_el2.html">SCTLR2_EL2</a>:
        System Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr2_el3.html">SCTLR2_EL3</a>:
        System Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr_el1.html">SCTLR_EL1</a>:
        System Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr_el2.html">SCTLR_EL2</a>:
        System Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sctlr_el3.html">SCTLR_EL3</a>:
        System Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-scxtnum_el0.html">SCXTNUM_EL0</a>:
        EL0 Read/Write Software Context Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-scxtnum_el1.html">SCXTNUM_EL1</a>:
        EL1 Read/Write Software Context Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-scxtnum_el2.html">SCXTNUM_EL2</a>:
        EL2 Read/Write Software Context Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-scxtnum_el3.html">SCXTNUM_EL3</a>:
        EL3 Read/Write Software Context Number</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sder32_el2.html">SDER32_EL2</a>:
        AArch32 Secure Debug Enable Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sder32_el3.html">SDER32_EL3</a>:
        AArch32 Secure Debug Enable Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smcr_el1.html">SMCR_EL1</a>:
        SME Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smcr_el2.html">SMCR_EL2</a>:
        SME Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smcr_el3.html">SMCR_EL3</a>:
        SME Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smidr_el1.html">SMIDR_EL1</a>:
        Streaming Mode Identification Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smprimap_el2.html">SMPRIMAP_EL2</a>:
        Streaming Mode Priority Mapping Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-smpri_el1.html">SMPRI_EL1</a>:
        Streaming Mode Priority Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmaccessr_el1.html">SPMACCESSR_EL1</a>:
        System Performance Monitors Access Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmaccessr_el2.html">SPMACCESSR_EL2</a>:
        System Performance Monitors Access Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmaccessr_el3.html">SPMACCESSR_EL3</a>:
        System Performance Monitors Access Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmcfgr_el1.html">SPMCFGR_EL1</a>:
        System Performance Monitors Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmcgcrn_el1.html">SPMCGCR&lt;n&gt;_EL1</a>:
        Counter Group Configuration Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmcntenclr_el0.html">SPMCNTENCLR_EL0</a>:
        System Performance Monitors Count Enable Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmcntenset_el0.html">SPMCNTENSET_EL0</a>:
        System Performance Monitors Count Enable Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmcr_el0.html">SPMCR_EL0</a>:
        System Performance Monitor Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmdevaff_el1.html">SPMDEVAFF_EL1</a>:
        System Performance Monitors Device Affinity Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmdevarch_el1.html">SPMDEVARCH_EL1</a>:
        System Performance Monitors Device Architecture Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmevcntrn_el0.html">SPMEVCNTR&lt;n&gt;_EL0</a>:
        System Performance Monitors Event Count Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmevfilt2rn_el0.html">SPMEVFILT2R&lt;n&gt;_EL0</a>:
        System Performance Monitors Event Filter Control Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmevfiltrn_el0.html">SPMEVFILTR&lt;n&gt;_EL0</a>:
        System Performance Monitors Event Filter Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmevtypern_el0.html">SPMEVTYPER&lt;n&gt;_EL0</a>:
        System Performance Monitors Event Type Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmiidr_el1.html">SPMIIDR_EL1</a>:
        Implementation Identification Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmintenclr_el1.html">SPMINTENCLR_EL1</a>:
        System Performance Monitors Interrupt Enable Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmintenset_el1.html">SPMINTENSET_EL1</a>:
        System Performance Monitors Interrupt Enable Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmovsclr_el0.html">SPMOVSCLR_EL0</a>:
        System Performance Monitors Overflow Flag Status Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmovsset_el0.html">SPMOVSSET_EL0</a>:
        System Performance Monitors Overflow Flag Status Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmrootcr_el3.html">SPMROOTCR_EL3</a>:
        System Performance Monitors Root and Realm Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmscr_el1.html">SPMSCR_EL1</a>:
        System Performance Monitors Secure Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spmselr_el0.html">SPMSELR_EL0</a>:
        System Performance Monitors Select Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsel.html">SPSel</a>:
        Stack Pointer Select</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_abt.html">SPSR_abt</a>:
        Saved Program Status Register (Abort mode)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_el1.html">SPSR_EL1</a>:
        Saved Program Status Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_el2.html">SPSR_EL2</a>:
        Saved Program Status Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_el3.html">SPSR_EL3</a>:
        Saved Program Status Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_fiq.html">SPSR_fiq</a>:
        Saved Program Status Register (FIQ mode)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_irq.html">SPSR_irq</a>:
        Saved Program Status Register (IRQ mode)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-spsr_und.html">SPSR_und</a>:
        Saved Program Status Register (Undefined mode)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sp_el0.html">SP_EL0</a>:
        Stack Pointer (EL0)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sp_el1.html">SP_EL1</a>:
        Stack Pointer (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sp_el2.html">SP_EL2</a>:
        Stack Pointer (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-sp_el3.html">SP_EL3</a>:
        Stack Pointer (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ssbs.html">SSBS</a>:
        Speculative Store Bypass Safe</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-svcr.html">SVCR</a>:
        Streaming Vector Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tco.html">TCO</a>:
        Tag Check Override</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tcr2_el1.html">TCR2_EL1</a>:
        Extended Translation Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tcr2_el2.html">TCR2_EL2</a>:
        Extended Translation Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tcr_el1.html">TCR_EL1</a>:
        Translation Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tcr_el2.html">TCR_EL2</a>:
        Translation Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tcr_el3.html">TCR_EL3</a>:
        Translation Control Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tfsre0_el1.html">TFSRE0_EL1</a>:
        Tag Fault Status Register (EL0).</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tfsr_el1.html">TFSR_EL1</a>:
        Tag Fault Status Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tfsr_el2.html">TFSR_EL2</a>:
        Tag Fault Status Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tfsr_el3.html">TFSR_EL3</a>:
        Tag Fault Status Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidr2_el0.html">TPIDR2_EL0</a>:
        EL0 Read/Write Software Thread ID Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidrro_el0.html">TPIDRRO_EL0</a>:
        EL0 Read-Only Software Thread ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidr_el0.html">TPIDR_EL0</a>:
        EL0 Read/Write Software Thread ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidr_el1.html">TPIDR_EL1</a>:
        EL1 Software Thread ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidr_el2.html">TPIDR_EL2</a>:
        EL2 Software Thread ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-tpidr_el3.html">TPIDR_EL3</a>:
        EL3 Software Thread ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbbaser_el1.html">TRBBASER_EL1</a>:
        Trace Buffer Base Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbidr_el1.html">TRBIDR_EL1</a>:
        Trace Buffer ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trblimitr_el1.html">TRBLIMITR_EL1</a>:
        Trace Buffer Limit Address Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbmar_el1.html">TRBMAR_EL1</a>:
        Trace Buffer Memory Attribute Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbmpam_el1.html">TRBMPAM_EL1</a>:
        Trace Buffer MPAM Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbptr_el1.html">TRBPTR_EL1</a>:
        Trace Buffer Write Pointer Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbsr_el1.html">TRBSR_EL1</a>:
        Trace Buffer Status/syndrome Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trbtrg_el1.html">TRBTRG_EL1</a>:
        Trace Buffer Trigger Counter Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcacatrn.html">TRCACATR&lt;n&gt;</a>:
        Address Comparator Access Type Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcacvrn.html">TRCACVR&lt;n&gt;</a>:
        Address Comparator Value Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcauthstatus.html">TRCAUTHSTATUS</a>:
        Authentication Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcauxctlr.html">TRCAUXCTLR</a>:
        Auxiliary Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcbbctlr.html">TRCBBCTLR</a>:
        Branch Broadcast Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcccctlr.html">TRCCCCTLR</a>:
        Cycle Count Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccidcctlr0.html">TRCCIDCCTLR0</a>:
        Context Identifier Comparator Control Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccidcctlr1.html">TRCCIDCCTLR1</a>:
        Context Identifier Comparator Control Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccidcvrn.html">TRCCIDCVR&lt;n&gt;</a>:
        Context Identifier Comparator Value Registers &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcclaimclr.html">TRCCLAIMCLR</a>:
        Claim Tag Clear Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcclaimset.html">TRCCLAIMSET</a>:
        Claim Tag Set Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccntctlrn.html">TRCCNTCTLR&lt;n&gt;</a>:
        Counter Control Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccntrldvrn.html">TRCCNTRLDVR&lt;n&gt;</a>:
        Counter Reload Value Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trccntvrn.html">TRCCNTVR&lt;n&gt;</a>:
        Counter Value Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcconfigr.html">TRCCONFIGR</a>:
        Trace Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcdevarch.html">TRCDEVARCH</a>:
        Device Architecture Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcdevid.html">TRCDEVID</a>:
        Device Configuration Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trceventctl0r.html">TRCEVENTCTL0R</a>:
        Event Control 0 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trceventctl1r.html">TRCEVENTCTL1R</a>:
        Event Control 1 Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcextinselrn.html">TRCEXTINSELR&lt;n&gt;</a>:
        External Input Select Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr0.html">TRCIDR0</a>:
        ID Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr1.html">TRCIDR1</a>:
        ID Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr10.html">TRCIDR10</a>:
        ID Register 10</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr11.html">TRCIDR11</a>:
        ID Register 11</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr12.html">TRCIDR12</a>:
        ID Register 12</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr13.html">TRCIDR13</a>:
        ID Register 13</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr2.html">TRCIDR2</a>:
        ID Register 2</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr3.html">TRCIDR3</a>:
        ID Register 3</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr4.html">TRCIDR4</a>:
        ID Register 4</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr5.html">TRCIDR5</a>:
        ID Register 5</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr6.html">TRCIDR6</a>:
        ID Register 6</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr7.html">TRCIDR7</a>:
        ID Register 7</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr8.html">TRCIDR8</a>:
        ID Register 8</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcidr9.html">TRCIDR9</a>:
        ID Register 9</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcimspec0.html">TRCIMSPEC0</a>:
        IMP DEF Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcimspecn.html">TRCIMSPEC&lt;n&gt;</a>:
        IMP DEF Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcitecr_el1.html">TRCITECR_EL1</a>:
        Instrumentation Trace Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcitecr_el2.html">TRCITECR_EL2</a>:
        Instrumentation Trace Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trciteedcr.html">TRCITEEDCR</a>:
        Instrumentation Trace Extension External Debug Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcoslsr.html">TRCOSLSR</a>:
        Trace OS Lock Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcprgctlr.html">TRCPRGCTLR</a>:
        Programming Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcqctlr.html">TRCQCTLR</a>:
        Q Element Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcrsctlrn.html">TRCRSCTLR&lt;n&gt;</a>:
        Resource Selection Control Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcrsr.html">TRCRSR</a>:
        Resources Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcseqevrn.html">TRCSEQEVR&lt;n&gt;</a>:
        Sequencer State Transition Control Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcseqrstevr.html">TRCSEQRSTEVR</a>:
        Sequencer Reset Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcseqstr.html">TRCSEQSTR</a>:
        Sequencer State Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcssccrn.html">TRCSSCCR&lt;n&gt;</a>:
        Single-shot Comparator Control Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcsscsrn.html">TRCSSCSR&lt;n&gt;</a>:
        Single-shot Comparator Control Status Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcsspcicrn.html">TRCSSPCICR&lt;n&gt;</a>:
        Single-shot Processing Element Comparator Input Control Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcstallctlr.html">TRCSTALLCTLR</a>:
        Stall Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcstatr.html">TRCSTATR</a>:
        Trace Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcsyncpr.html">TRCSYNCPR</a>:
        Synchronization Period Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trctraceidr.html">TRCTRACEIDR</a>:
        Trace ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trctsctlr.html">TRCTSCTLR</a>:
        Timestamp Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvictlr.html">TRCVICTLR</a>:
        ViewInst Main Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcviiectlr.html">TRCVIIECTLR</a>:
        ViewInst Include/Exclude Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvipcssctlr.html">TRCVIPCSSCTLR</a>:
        ViewInst Start/Stop PE Comparator Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvissctlr.html">TRCVISSCTLR</a>:
        ViewInst Start/Stop Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvmidcctlr0.html">TRCVMIDCCTLR0</a>:
        Virtual Context Identifier Comparator Control Register 0</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvmidcctlr1.html">TRCVMIDCCTLR1</a>:
        Virtual Context Identifier Comparator Control Register 1</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trcvmidcvrn.html">TRCVMIDCVR&lt;n&gt;</a>:
        Virtual Context Identifier Comparator Value Register &lt;n&gt;</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trfcr_el1.html">TRFCR_EL1</a>:
        Trace Filter Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-trfcr_el2.html">TRFCR_EL2</a>:
        Trace Filter Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ttbr0_el1.html">TTBR0_EL1</a>:
        Translation Table Base Register 0 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ttbr0_el2.html">TTBR0_EL2</a>:
        Translation Table Base Register 0 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ttbr0_el3.html">TTBR0_EL3</a>:
        Translation Table Base Register 0 (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ttbr1_el1.html">TTBR1_EL1</a>:
        Translation Table Base Register 1 (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-ttbr1_el2.html">TTBR1_EL2</a>:
        Translation Table Base Register 1 (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-uao.html">UAO</a>:
        User Access Override</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vbar_el1.html">VBAR_EL1</a>:
        Vector Base Address Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vbar_el2.html">VBAR_EL2</a>:
        Vector Base Address Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vbar_el3.html">VBAR_EL3</a>:
        Vector Base Address Register (EL3)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vdisr_el2.html">VDISR_EL2</a>:
        Virtual Deferred Interrupt Status Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vmecid_a_el2.html">VMECID_A_EL2</a>:
        Alternate MECID for EL1&amp;0 stage 2 translation regime</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vmecid_p_el2.html">VMECID_P_EL2</a>:
        Primary MECID for EL1&amp;0 stage 2 translation regime</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vmpidr_el2.html">VMPIDR_EL2</a>:
        Virtualization Multiprocessor ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vncr_el2.html">VNCR_EL2</a>:
        Virtual Nested Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vpidr_el2.html">VPIDR_EL2</a>:
        Virtualization Processor ID Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vsesr_el2.html">VSESR_EL2</a>:
        Virtual SError Exception Syndrome Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vstcr_el2.html">VSTCR_EL2</a>:
        Virtualization Secure Translation Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vsttbr_el2.html">VSTTBR_EL2</a>:
        Virtualization Secure Translation Table Base Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vtcr_el2.html">VTCR_EL2</a>:
        Virtualization Translation Control Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-vttbr_el2.html">VTTBR_EL2</a>:
        Virtualization Translation Table Base Register</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-zcr_el1.html">ZCR_EL1</a>:
        SVE Control Register (EL1)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-zcr_el2.html">ZCR_EL2</a>:
        SVE Control Register (EL2)</span></p></div>
    <div><p class="iformindex"><span class="insnheading"><a href="AArch64-zcr_el3.html">ZCR_EL3</a>:
        SVE Control Register (EL3)</span></p></div>
  <hr/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:16</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
  
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